cystech electronics corp. spec. no. : c323n3 issued date : 2013.12.27 revised date : page no. : 1/8 MTA55N02N3 cystek product specification 20v n-channel enhancement mode mosfet MTA55N02N3 bv dss 20v i d 3.6a 29m (typ.) r dson(max) @v gs =4.5v, i d =3.6a 39m (typ.) r dson(max) @v gs =2.5v, i d =3.1a features ? simple drive requirement ? small package outline ? capable of 2.5v gate drive ? pb-free lead plating and halogen-free package symbol outline ordering information device package shipping MTA55N02N3-0-t1-g sot-23 (pb-free lead plating an d halogen-free package) 3000 pcs / tape & reel MTA55N02N3 sot-23 d s g gate s source d drain g environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pc s / tape & reel,7? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c323n3 issued date : 2013.12.27 revised date : page no. : 2/8 MTA55N02N3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 20 v gate-source voltage v gs 12 v continuous drain current @v gs =4.5v, t a =25 c (note 3) 3.6 a continuous drain current @v gs =4.5v, t a =70 c (note 3) i d 2.9 a pulsed drain current (notes 1, 2) i dm 10 a p d 1.38 (note 3) w maximum power dissipation@ t a =25 linear derating factor 0.01 w/ c operating junction and storage temperature tj, tstg -55~+150 c note : 1. pulse width limited by maximum junction temperature. 2. pulse width 300 s, duty cycle 2%. 3. surface mounted on 1 in2 copper pad of fr-4 board, t 5s; 270 c/w when mounted on minimum copper pad. thermal performance parameter symbol limit unit thermal resistance, junction-to-ambient, max r ja 90 c/w thermal resistance, junction-to-case, max r jc 80 c/w note : surface mounted on 1 in2 copper pad of fr-4 board, t 5s; 270 c/w when mounted on minimum copper pad. electrical characteristics (tj=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions static bv dss 20 - - v v gs =0, i d =250 a ? bv dss / ? tj - 0.1 - v/ c reference to 25c, i d =1ma v gs(th) 0.35 0.5 0.7 v v ds =v gs , i d =250 a i gss - - 100 na v gs = 12v, v ds =0 - - 1 a v ds =20v, v gs =0 i dss - - 10 a v ds =20v, v gs =0 (tj=70 c) - 29 55 i d =3.6a, v gs =4.5v *r ds(on) - 39 70 m i d =3.1a, v gs =2.5v *g fs - 7.5 - s v ds =5v, i d =3.6a dynamic ciss - 440 - coss - 61 - crss - 59 - pf v ds =10v, v gs =0, f=1mhz
cystech electronics corp. spec. no. : c323n3 issued date : 2013.12.27 revised date : page no. : 3/8 MTA55N02N3 cystek product specification t d(on) - 4.5 - t r - 7.4 - t d(off) - 19 - t f - 7.2 - ns v ds =10v, i d =3.6a, v gs =5v r g =6 , r d =2.8 qg - 4.4 - qgs - 0.7 - qgd - 1.7 - nc v ds =10v, i d =3.6a, v gs =4.5v source-drain diode *v sd - 0.8 1.2 v v gs =0v, i s =1.6a i s - - 1 i sm - - 10 a v d =v g =0v, v s =1.2v *pulse test : pulse width 300 s, duty cycle 2% recommended soldering footprint
cystech electronics corp. spec. no. : c323n3 issued date : 2013.12.27 revised date : page no. : 4/8 MTA55N02N3 cystek product specification typical characteristics typical output characteristics 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 v ds , drain-source voltage(v) i d , drain current(a) 4.5v 3.5v 3v 2.5v v gs =1.5v v gs =2v static drain-source on-resistance vs ambient temperature 0 5 10 15 20 25 30 35 40 45 50 -60 -20 20 60 100 140 180 t a , ambient temperature(c) r ds(on) , static drain-source on-state resistance(m) i d =3.6a, v gs =4.5v static drain-source on-state resistance vs drain current 10 100 1000 10000 1 10 100 1000 10000 i d , drain current(ma) r ds(on) , static drain-source on-state resistance(m) v gs =1.5v v gs =4.5v v gs =2v v gs =2.5v forward drain current vs source-drain voltage 1 10 100 1000 10000 0.4 0.6 0.8 1 1.2 1.4 v sd , source drain voltage(v) i f , forward drain current(ma) tj=25c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 50 100 150 200 250 300 350 400 450 500 012345 v gs , gate-source voltage(v) r ds(on ), static drain-source on- state resistance(m) i d =3.1a t a =25c capacitance vs reverse voltage 10 100 1000 0 2 4 6 8 101214161820 v ds , drain-to-source voltage(v) capacitance-(pf) ciss coss crss f=1mhz
cystech electronics corp. spec. no. : c323n3 issued date : 2013.12.27 revised date : page no. : 5/8 MTA55N02N3 cystek product specification typical characteristics(cont.) maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current (a) r ds( on) limited ta=25c, single pulse, v gs =10v, tj=150c dc 100ms 10ms 1ms 100 s gate threshold voltage vs ambient temperature 0.2 0.4 0.6 0.8 1 -60 -20 20 60 100 140 180 junction temperature-tj(c) v gs( th) , gate sourcethreshold voltage-(v) i d =250 a gate charge characteristics 0 2 4 6 8 10 0246810 qg, total gate charge(nc) v gs , gate-source voltage(v) v ds =10v i d =3.6a maximum drain current vs junction temperature 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =10v transient thermal response curves 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 t 1 , square wave pulse duration(s) r(t), normalized effectivetransient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =90 c/w
cystech electronics corp. spec. no. : c323n3 issued date : 2013.12.27 revised date : page no. : 6/8 MTA55N02N3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c323n3 issued date : 2013.12.27 revised date : page no. : 7/8 MTA55N02N3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c323n3 issued date : 2013.12.27 revised date : page no. : 8/8 MTA55N02N3 cystek product specification sot-23 dimension *: typical 3-lead sot-23 plastic surface mounted package cystek package code: n3 marking: te .2306 style: pin 1.gate 2.source 3.drain inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1102 0.1204 2.80 3.04 j 0.0032 0.0079 0.08 0.20 b 0.0472 0.0669 1.20 1.70 k 0.0118 0.0266 0.30 0.67 c 0.0335 0.0512 0.89 1.30 l 0.0335 0.0453 0.85 1.15 d 0.0118 0.0197 0.30 0.50 s 0.0830 0.1161 2.10 2.95 g 0.0669 0.0910 1.70 2.30 v 0.0098 0.0256 0.25 0.65 h 0.0000 0.0040 0.00 0.10 l1 0.0118 0.0197 0.30 0.50 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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